This invention is in the field of solid-state non-volatile memory, and is more specifically directed to the detection of failed memory cells in such memory.
As well known in the art, “flash” memories are electrically-erasable and rewritable semiconductor memory devices that can be erased at once (in a “flash”) on a chip-wide basis, or in smaller units referred to as blocks. As such, flash memory has become especially popular for applications in which non-volatility (i.e., data retention after removal of power) of the stored data is essential, and in which rewriting of the data is required, but where the frequency of such rewriting is relatively low. Popular applications of flash memory include portable audio players, “SIM” card storage of telephone numbers and phone activity in cellular telephone handsets, “thumbkey” removable storage devices for computers and workstations, storage devices for digital cameras, and the like.
An important recent advance in semiconductor non-volatile memory technology is the arrangement of the flash memory cells as “NAND” memory rather than as “NOR” memory. As known in the art, NOR flash memory refers to the conventional arrangement of a column of memory cells in parallel between a bit line and a source line. Access of a specific cell in a NOR column is made by driving its word line (control gate) active while holding the other cells in the column off, so that the current between the bit line and source line is determined by the state of the accessed cell. Memory cells in a column of NAND memory, on the other hand, are connected in series between the bit line and the source line. Accessing of a specific cell in a NAND column thus requires turning on all of the cells in the column with active word line levels, and applying an intermediate word line level to the cell to be accessed, such that the current between the bit line and source line is, again, determined by the state of the accessed cell. As well known in the art, the chip area required per bit of NAND flash memory is much reduced from the area per bit of NOR flash memory, primarily because fewer conductors (and therefore contacts) are required for a column of NAND memory relative to NOR memory; in addition, access transistors can be shared among a large number of cells in the NAND arrangement. Additionally, conventional NAND flash memory is conveniently accessed serially, for example by sequentially accessing the contents of cells sharing a word line (i.e., within a row), rather than as a random access memory as in the case of NOR memory. NAND memory is thus especially well-suited for storing music and video, and for other file storage applications.
Another important recent advance in the field of flash memory is referred to in the art as the multilevel cell (MLC). According to this approach, more than two data states are made possible for each memory cell, simply by more finely controlling the programming of the cell. In conventional binary data storage, each memory cell is programmed into either a “0” or a “1” state. Reading of such binary cells is accomplished by applying a single control voltage to the control gate of the addressed memory cell so that the transistor conducts if programmed to a “1” state, but remains off in the “0” state; sensing of the conduction through the addressed memory cell thus returns the programmed state of the cell. In contrast, according to a typical example of the MLC approach, four possible states are defined for each memory cell, typically corresponding to binary values 00, 01, 10, 11. In effect, the two intermediate states correspond to two levels of partial programming of the cell between the fully erased and fully programmed states. Some implementations of MLC flash memory with up to eight possible states, or three bits, per cell are known. The ability to store two or three bits of data on each memory cell of course doubles or triples the data capacity of a flash memory chip for a given number of memory cells. Examples of MLC flash memory cells and memories including such MLC cells are described in U.S. Pat. No. 5,172,338, and U.S. Pat. No. 6,747,892 B2, both commonly assigned herewith and incorporated herein by this reference.
The combination of MLC technology with the efficiencies of NAND flash memory architectures has resulted in significantly reduced cost per bit for semiconductor non-volatile storage, as well as improved system reliability, and a higher data capacity and system functionality for a given form factor.
Modern flash memory devices, particularly those of the NAND architecture and involving MLC cells, are arranged in “blocks” and “pages”. A block refers to an erase unit, and defines a group of cells that are simultaneously erased in a single erase operation. Typically, a block of cells is smallest group of cells that can be erased. A page refers to a programming unit, and defines a group of cells that are simultaneously programmed, or written, in a single programming operation. Each block typically includes multiple pages. Generally, the arrangement of cells into pages and blocks is based on the physical realization of the memory array. For example, in many NAND memory arrays, a page of memory cells is defined by those cells that share the same word line, and a block is defined by those pages residing in the same “NAND” chain. For example, if a NAND chain includes thirty-two memory cells in series, a block will typically include thirty-two pages, or an integer multiple of thirty-two pages. In some NAND memory arrays, one word line can be shared by cells for two pages; the data for a first page is stored in the cells of even-numbered columns, while the data for a second page is stored in the cells of odd-numbered columns along that word line. Other arrangements are also possible. Conventional MLC flash memories are often configured so that one physical page corresponds to two or more logical pages, each logical page corresponding to one of the bit positions of the multiple-bit data. For example, in a four-state MLC memory array, each physical page will store data for two logical pages, which are referred to as the “upper” and “lower” pages.
Historically, the organization of data stored in a flash memory has followed the file systems used in connection with magnetic disk storage, and as such is based on “sectors”. A sector is typically a group of data of a fixed size, for example, 512 bytes of user data plus some number of bytes of overhead. In many modern file systems, the operating system of the computer or other host system arranges data into sectors, and writes data to and reads data from non-volatile storage on a sector-by-sector basis. To permit convenient use of flash memory devices as non-volatile storage devices in such systems and applications, many modern flash memories handle data in a similar fashion, mapping logical “sector” addresses to physical addresses in the flash memory array.
In recent years, the sizes and capacities of flash memory devices have greatly increased, resulting in memory arrays of more than 4 billion cells. In such arrays, a single word line may extend to over 32000 memory cells, placing that many memory cells within the same page, or programming unit. In such large scale flash memories, therefore, each page now includes multiple sectors. As such, the units of data handled by the host system (i.e., “sectors”) are smaller than the smallest programming unit in the flash memory device. Typically, however, the multiple sectors of data that comprise a page of the flash memory will be sequentially communicated to the flash memory, and will be simultaneously programmed into a page of the flash memory in a single operation.
By way of further background, the use of error correction coding (ECC) in mass data storage devices and storage systems, as well as in data communications systems, is well known. As fundamental in this art, error correction coding involves the storage or communication of additional bits (commonly referred to as parity bits, code bits, checksum digits, ECC bits, etc.) that are determined or calculated from the “payload” data bits being encoded. For example, the storage of error correction coded data in a memory resource involves the encoding of a code word including the actual data and the additional code bits, using a selected code. Retrieval of the stored data involves the decoding of the stored code word according to the same code as used to encode the stored code word. Because the code bits “over-specify” the actual data portion of the code word, some number of errored bits can be tolerated, without any loss of actual data evident after decoding.
Many ECC coding schemes are well known in the art. These conventional error correction codes are especially useful in large scale memories, including flash memories, because of the substantial impact on manufacturing yield and device reliability that such coding schemes can provide, rendering devices that have a few non-programmable or defective cells as useable. Of course, a tradeoff exists between the yield savings and the cost of providing additional memory cells to store the code bits (i.e., the code “rate”). As such, some ECC codes are better suited for flash memory devices than others; generally, ECC codes for flash memory devices tend to have higher code rates (i.e., a lower ratio of code bits to data bits) than the codes used in data communications applications (which may have code rates as low as ½). Examples of well-known ECC codes commonly used in connection with flash memory storage include Reed-Solomon codes, other BCH codes, Hamming codes, and the like. Typically, the error correction codes used in connection with flash memory storage are “systematic”, in that the data portion of the eventual code word is unchanged from the actual data being encoded, with the code or parity bits appended to the data bits to form the complete code word.
The particular parameters for a given error correction code include the type of code, the size of the block of actual data from which the code word is derived, and the overall length of the code word after encoding. For example, a typical BCH code applied to a sector of 512 bytes (4096 bits) of data can correct up to four errored bits, if at least 60 ECC or parity bits are used. Reed-Solomon codes are a subset of BCH codes, and are also commonly used for error correction. For example, a typical Reed-Solomon code can correct up to four errors in a 512 byte sector of data, using about 72 ECC bits.
In the flash memory context, error correction coding provides substantial improvement in manufacturing yield, as well as in the reliability of the flash memory over time. These improvements are attained at a cost of the additional memory cells required for storing the ECC or parity bits (rather than storing actual data). Error correction coding is especially beneficial in flash memories, considering that flash memory cells degrade as the result of “wear” from previous programming and erase cycles. In addition, flash memories of the MLC type especially benefit from error correction coding, because of the narrow threshold voltage margins required to resolve more than two logic states from each memory cell.
By way of further background, the programming and erasing of conventional flash memory devices now typically involves the verification of the state of the memory cells being programmed or erased, to ensure that the desired state has been reached for each of the cells subject to the operation. Indeed, considering that the programming and erasing of flash memory cells are typically performed by the application of a sequence of pulses of the appropriate voltages, and also considering that the pulse sequences consume substantial time and power, many flash memories now include verification operations during the programming or erasing operations themselves. For example, the programming of a page of memory cells is typically performed by applying a programming pulse, and then verifying the programmed cells against a desired “verify” voltage for the data level being programmed. If not all of the memory cells verify to the desired level after a first pulse, the programming pulse is repeated (often at a higher voltage), and the cells are verified again. Upon all of the memory cells reaching the desired program level, the programming operation is terminated.
Verification is also typically performed in the erasing of a block of flash memory cells, with additional erase pulses applied as necessary to ensure all cells are erased. In general, for NAND flash memories, erase verification is typically performed by applying a selected control gate voltage to all of the word lines of the block being erased, to determine whether any of the cells conduct at that control gate voltage. Because the threshold voltages of erased cells are typically below 0 volts, and because the application of negative word line voltages is not desirable, the verifying of negative erase voltages is often done by way of a low or zero voltage on the word lines, with the common source lines biased to effectively place a negative gate-to-source voltage at each memory cell in the NAND chain. The verify voltages typically differ from the control gate voltages applied in read cycles, to provide operating margin within the device. A similar approach is used for verifying the so-called “soft” programmed states of erased NAND cells; “soft” programming refers to the conventional operation of slightly programming erased flash memory cells, to prevent some or all of the cells from being too deeply erased.
In modern NAND flash memory devices that use floating-gate metal-oxide-semiconductor (MOS) transistors as memory cells, the programming operation involves the applying of a program voltage to the control gate of the transistor, and the grounding of its source-drain regions (i.e., the bit lines). This bias condition causes tunneling of electrons from the channel region through the gate dielectric and into the floating gate, where the electrons accumulate. The accumulated electrons negatively charge the floating gate, raising the threshold voltage of the memory cell (i.e., the voltage to which the control gate must be biased for conduction).
An example of a sequence of the program voltage pulses that are applied to the control gate of a flash memory cell is illustrated in FIG. 1a. As shown in FIG. 1a, the pulsed control gate voltage increases with each successive pulse by a predetermined step increment (e.g., 0.2 to 0.5 volts; of course, the step voltage can be larger or smaller than this range, depending on the application). After each programming pulse (or group of pulses, if desired), a verify operation is performed to determine whether each cell has been adequately programmed to the desired threshold voltage. This verify operation interrogates the programming level of each cell in the page being programmed (i.e., each cell that is intended to be programmed, depending on the input data) in parallel, to determine whether the threshold voltage of the cell is equal to or greater than a verify level corresponding to the data state being programmed. If not, that memory cell is subjected to an additional programming pulse or sequence of pulses.
A typical way of verifying programming is to test the conduction of each cell at a specific compare point that is set by a control gate voltage. Those cells that have previously been verified as sufficiently programmed are locked out, for example, by raising the bit line voltage for those cells in the page being programmed to a high level (e.g., the voltage of the Vdd power supply), to stop the programming process for those cells. Those cells that are not yet sufficiently programmed receive the next higher voltage pulse in the programming sequence of FIG. 1a, followed by another verify operation.
For example, FIG. 1b presents plot 5 of threshold voltage Vth over time, for a specific cell in a page being programmed by the pulse sequence of FIG. 1a. Plot 5 shows that the threshold voltage increases for this cell with each pulse of the programming voltage Vpgm applied to its control gate. At time t1, following a first pulse (or sequence of pulses) at programming voltage Vpgm=V1, the threshold voltage Vth has increased slightly from its unprogrammed (erased) state Ve, as shown in FIG. 1b. However, because this threshold voltage remains below the verify voltage Vverify(1) for a “1” data state, which is the desired programmed state in this example. Accordingly, a second pulse (or sequence of pulses) are applied to this cell, at a slightly higher programming voltage Vpgm=V2. Typically, the voltage step from one programming voltage Vpgm level to the next (e.g., V2-V1) may be about 0.2 to 0.5 volts. The programmed cell is then again verified at time t2, and the sequence continues. In the example of FIGS. 1a and 1b, the cell being programmed by the sequence of FIG. 1a reaches (and exceeds) the verify voltage Vverify(1) for the desired data state at verify time t4. This cell is then “locked out” from further programming as mentioned above, and does not receive the next higher programming voltage Vpgm=V5. Other cells in the same page that are being programmed to this data state may receive additional pulses.
Additional description of programming and verification operations as known in the art are described in commonly assigned U.S. Pat. No. 6,888,758 B1, and in copending U.S. patent application Ser. No. 10/314,055, now published as U.S. Patent Application Publication No. 2004/0109362, both incorporated herein by this reference.
As is well known in this art, some memory cells are slower to program or erase than others, because of manufacturing variations among those cells, because those cells were previously erased to a lower threshold voltage than others, because of uneven wear among the cells within a page, or the like. And, of course, some cells cannot be programmed or erased whatsoever, because of a manufacturing defect. As mentioned above, error correction coding provides the capability of tolerating some number of slow or failed cells, while still maintaining the memory usable. In some applications, a page of data is programmed by repeatedly applying programming pulses until all memory cells on that page verify to the desired programmed state. In these applications, programming terminates if a maximum number of programming pulses is reached prior to successful verifying of the programmed page, following which the number of cells that have not yet been verified to the desired state is compared with a threshold value, which depends on the capability of the error correction coding that will be used in the reading of data from that page. In other applications in which the error correction is sufficiently robust, programming and erasing time is saved by terminating the sequence of programming or erasing pulses upon the number of slow (or failed) cells that are not yet fully programmed or erased being fewer than the number of bits that are correctable.
FIG. 2a illustrates the architecture of a conventional flash memory device, with reference to flash memory device 2, which includes the capability of performing verify operations during the programming and erasing of its memory cells. Within flash memory device 2, flash memory array 11 includes flash memory cells arranged in rows and columns. In this conventional flash memory, as is typical, rows of memory cells correspond to those memory cells sharing a common word line, and as such each row defines a page, which is the programming unit for the device. As discussed above, the physical page defined by a word line can correspond to multiple logical pages, for example with even- and odd-numbered cells corresponding to respective logical pages, or with each cell storing upper and lower page data as in conventional MLC arrays. The columns of memory cells share bit lines; in conventional NAND flash memories, as mentioned above, those pages of memory cells that are within the same NAND chains are referred to as a block, which is the erase unit. And, as is also well known in the art, flash memory device 2 may have multiple arrays 10, which are often referred to as “planes” in the memory, such planes being separately (or simultaneously) addressable as one another.
Flash memory device 2 includes control logic circuitry 20, which receives control signals from external terminals as shown, such control signals including chip select signals, latch enable strobes for address, commands, and data, read/write control signals, and the like, as conventional for flash memory devices. External input/output terminals (I/O) receive address, command, and input data for flash memory device 2, and are also used to present output data from flash memory device 2, as conventional in the art. As such, terminals I/O are also connected to control logic circuitry 20, which includes the necessary and appropriate registers for address and command values. Based on such address values as received from terminals I/O, control logic circuitry 20 generates the appropriate signals to row decode 12 for selecting the desired page of flash memory array 11 that is to be addressed. NOR-type flash memories may also include a column decoder (not shown), so that a single byte or bit within the addressed page can be selected.
Data is read from the addressed memory cells by way of row decode 12 selecting a page to be read. In a read operation (indicated by a control signal program/read from control logic 20), sense amplifiers 15 detect the states stored in the cells of the selected page, and forward those data via bus DB to data register 19 for output to terminals I/O, under the control and possible buffering of that data by control logic circuitry 20. Typically, one sense amplifier 15 is provided for each column of array 11, although in some flash memories one sense amplifier 15 may be provided for every two columns, with a single address bit determining which of the pair of columns (i.e., either the odd column or the even column) is to be sensed by that sense amplifier 15 in the read.
A write, or program, operation involves the receipt of data at terminals I/O and the transfer of that data to data register 19 (such transfer often involving buffering of the incoming data within control logic circuitry 20). This input data is forwarded to sense amplifiers 15 over bus DB. Sense amplifiers 15 in turn bias the bit lines of the cells in the selected page that are to be programmed with pulses of the appropriate programming voltages.
Flash memory device 2 performs verification of the programmed cells by row decode 12 applying the appropriate verify control voltage to the memory cells in the programmed page, and sense amplifiers 15 then sensing the state of the cells in that page to determine which cells in the page have been programmed beyond the verify threshold voltage. In this conventional arrangement, sense amplifiers 15 retain the data state that is being programmed to each cell. As such, each of sense amplifiers 15 compares the sensed data state to the desired data state, with sense amplifiers 15 as a group thus perform a bit-by-bit comparison (i.e., an exclusive-OR operation between the programmed state and the desired state) over the entire page. The results of the comparison performed by sense amplifiers 15 are applied to fail bit detector 16.
Fail bit detector 16 effectively counts the number of failed bits in the results forwarded by sense amplifiers 15. For purposes of this verification operation, the term “failed bits” refers to those memory cells that have not yet reached their desired programmed threshold voltage, as sensed by sense amplifiers 15 in response to the verify control gate voltage applied to the word line by row decode 12. For example, if the erased state of a memory cell corresponds to a “1” state (i.e., the threshold voltage of the memory cell is extremely low or negative), the programmed state corresponds to a “0”, or sufficiently high threshold voltage as to not turn on with the application of the verify control gate voltage. In this example, therefore, the data state to be programmed in selected memory cells of the currently selected page will be a “0”, and those cells that have been sufficiently programmed will have threshold voltages sufficiently high that the devices are off with the application of the verify voltage to their control gates (thus also exhibiting a “0” state). On the other hand, an inadequately programmed cell will still have a low threshold voltage (i.e., below the verify control gate voltage), and will thus conduct (i.e., present a “1” level) upon application of the verify control gate voltage, which will be opposite the desired programmed “0”.
In this conventional approach, fail bit detector 16 forwards the number of failed bits over the entire currently sensed page to control logic circuitry 20. As described above, in some applications, control logic circuitry 20 determines whether to apply an additional programming pulse by comparing this number of failed bits in the page against an “ignore bit” limit for the page. The ignore bit limit depends on the error correction coding of the data; if more memory cells than desired have not yet been sufficiently programmed (i.e., more failed bits than the ignore bit limit), programming continues. This iterative sequence continues either until the page is sufficiently programmed (i.e., the number of failed bits is below the ignore bit limit), or until a selected maximum number of programming loops have been performed, in which case the page is marked as unusable if too many cells in that page have not yet been adequately programmed. Also as described above, in other applications, programming is performed until all cells are verified as having reached their desired state, or until a specified maximum number of programming pulses have been carried out, following which the number of failed bits counted by fail bit detector 16 is compared against the ignore bit limit, to determine whether the page is usable after this programming operation.
As known in the art, this verification process is also useful in erasing a block of memory cells in flash memory array 11, considering that erasure requires the application of relatively high voltages to the memory cells, and is also generally performed in an iterative sequence of pulses. As mentioned above, however, the block is the typical erase unit, with each block having multiple pages (e.g., the number of pages corresponding to the number of cells in the NAND chain, for NAND flash memory). A similar operation as described above is performed to verify adequate erasing of the cells in the block (in effect, by sensing the number of columns within the block having cells that are not yet fully erased), with another iteration of the erase pulses applied if cells remain to be erased. In addition, a so-called “soft” programming operation may also be performed, to slightly program cells that have been erased so that deeply erased cells do not cause errors in other cells, for example by program disturb. The verify operation after such “soft” programming can be performed over an entire block, as described above, to ensure that the cells remain erased, but yet have threshold voltages within a “window” above that of deep erased cells. For multi-level programming cells (MLC), the programming sequences are repeated at different levels (sometimes referred to as “upper pages” and “lower pages”), to more precisely define a particular programming threshold level within the MLC constellation. Of course, verify operations are also repeated in this repeated programming operation, to ensure programming of the selected cells to within the desired threshold voltage window for the data state to be stored.
FIG. 2b illustrates the architecture of another conventional flash memory device, an example of which is described in commonly assigned U.S. Pat. No. 6,972,993 B2, issued Dec. 6, 2005 and incorporated herein by this reference. In addition to the capability of verifying programmed and erased states during the programming and erasing of its memory cells, as described above, additional circuitry is provided within flash memory device 2′ to verify programmed data states by way of read operations after such programming and erasing.
In this example, the data flow of flash memory device 2′, in a write or program operation, involves the receipt of data at terminals I/O, and the eventual transfer of that data to master data register 19 (such transfer often involving buffering of the incoming data within control logic circuitry 20). This input data is forwarded to slave data register 17, with a copy maintained in data compare register 18 (thus permitting master data register 19 to receive a next set of input data). As described in the above-incorporated U.S. Pat. No. 6,972,993 B2, by way of example, verification of the programmed cells is effected by row decode 12 applying the appropriate verify control voltage to the memory cells in the programmed page, and sense amplifiers 15 then sensing the state of the cells in that page to determine which cells in the page have been programmed beyond the verify threshold voltage. The sensed states for the cells in that page are stored in slave data register 17, while data compare register 18 retains a copy of the desired data to be programmed, as mentioned above. Slave data register 17 and data compare register 18 each forward their stored contents to comparator circuit 22, which performs a bit-by-bit comparison (exclusive-OR) of the two contents, forwarding the results to control logic circuitry 20. Control logic circuitry 20 then determines whether the number of cells in the programmed page that have failed verification exceed the ignore bit limit.
In some conventional flash memory applications, the program-and-verify operation is iteratively performed after each programming loop, until all of the cells being programmed in the page pass the verification. However, the counting of failed bits may not be performed until the terminal number of programming cycles is reached, because the fail bit count can be quite time consuming, if performed in every verify operation. In other, typically more advanced, flash memory applications, the counting of failed bits is not performed until a certain number of program-and-verify loops have been completed, because it is unlikely that the ignore bit limit will be met at that point. After that certain number of program-and-verify loops, the fail bit count operation is included with verification, for use in the decision of whether to continue programming the page.
Those skilled in the art will recognize that the increasing density of flash memory cells has resulted in very long word lines, with up to on the order of 32 k or more memory cells sharing a word line, and thus residing within the same page. Besides the desire to increase the capacity of a flash memory integrated circuit, it is desirable to include as many cells within a page to save time during programming. As evident from the above description, programming of flash memory cells can be a time consuming process, especially when verify operations are involved in the iterative programming of a page. However, the programming operation programs the cells within a page in parallel, so that a higher degree of parallelism (more cells per page) will improve the efficiency of the programming process.
On the other hand, host systems that utilize flash memory communicate in smaller units of data, for example by storing and retrieving “sectors” of data, analogously (or identically) in the same manner as accessing conventional magnetic disk drives. Because typical sector sizes are on the order of 512 bytes plus overhead (and plus ECC bits), flash memory pages typically include multiple sectors of data. FIG. 3 illustrates the arrangement of a conventional multi-sector page of data in flash memories. In this example, page 8 of FIG. 3 includes four sectors 100 through 103. Each sector 10 includes data portion 3, for storing user data or other data, such as the data generated by an application executing on a host system and communicated to the flash memory for storage. Header portion 5 stores control information for its sector, such control information including identifying information for its associated sector, and status information regarding the data in its associated data portion 3. ECC bit portion 4 stores the ECC or parity bits that are generated from the data in data portion 3 (and also possibly including header portion 5), and that are used in decoding the contents read from sector 10 to correct for any bit errors in that data. As evident from FIG. 3, in which each sector 10 includes its own ECC bit portion 4, error correction decoding is performed on a sector-by-sector basis in conventional flash memories. This error correction is convenient and useful because the sector is the desired unit of data transfer to and from the host system. For example, a typical number of bits correctable within a sector of 512 bytes, using a BCH or Reed-Solomon code is four.